Embodiments of the present invention relate generally to circuit synthesis, and more particularly to tracking and providing information regarding circuits such as registers that are removed during circuit synthesis.
Integrated circuits are often designed intending to be implemented using a field programmable gate array (FPGA.) During this design, a circuit schematic and corresponding netlist are generated by a circuit designer, who may also be referred to as a user. The netlist is then fitted to an FPGA, such that the FPGA implements the user-designed circuitry. This fitting is referred to as synthesis.
As a part of synthesizing a user design, registers are both duplicated (split) and removed (deleted). There are at least two reasons why a register may be removed or deleted during this process. First, a user may make a connection that the user understands will be corrected by the synthesizer, where the correction involves the removal of one or more registers. A second and more troublesome removal can occur when a user makes a connection or logic error in the circuit design.
As an example of the first case, a user may purposely misconnect a 16-bit bus driver to a 14-bit input port with the understanding that this will leave two registers dangling, where the two bus driver registers are not used. It will be the user's expectation that the synthesizer will correct this error and that these two extra registers will be removed or swept away during the synthesizing process. It is often convenient for the user to simply connect circuits in this way and allow the synthesis tool to react appropriately.
Unfortunately, unintended design errors also cause registers to be removed in a way that may be contrary to the user's desire. For example, a common mistake is to neglect to connect an external clock pin to a register's internal clock node. Since the clock input for the register is not driven, its output is stuck at ground. This causes the registers to be removed, as its clock input never toggles and thus the output of the register is independent of its input. As the iterative aspect of synthesis progresses, the removal of this register may result in further registers being removed from the design.
When a register is removed, particularly when it is due to an unintended design error, it is very desirable that the user knows that it was removed, as well as the reason why it was removed and further consequences of its removal. Thus, what is needed are circuits, methods, software, and apparatus that track register or other circuit removal and provide easy to read information regarding the reason for removal.